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fix 64bits ops using RDX:RAX and outputing in RDX

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Nopana_Eliyaan 2025-09-10 09:59:08 +02:00
parent 3ae4f24d8e
commit 7fb6a84ff6
1 changed files with 18 additions and 16 deletions
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34
vlib/v/gen/native/amd64.v
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@ -3026,8 +3026,8 @@ fn (mut c Amd64) assign_stmt(node ast.AssignStmt) {
c.g.expr(val) c.g.expr(val)
c.push(c.main_reg()) c.push(c.main_reg())
c.g.gen_left_value(left) c.g.gen_left_value(left)
c.mov_reg(Amd64Register.rdx, Amd64Register.rax) // effective address of the left expr c.mov_reg(Amd64Register.rbx, Amd64Register.rax) // effective address of the left expr
c.mov_deref(Amd64Register.rax, Amd64Register.rdx, var_type) // value of left expr c.mov_deref(Amd64Register.rax, Amd64Register.rbx, var_type) // value of left expr
c.pop(.rcx) // value of right expr c.pop(.rcx) // value of right expr
c.gen_type_promotion(node.right_types[0], var_type) c.gen_type_promotion(node.right_types[0], var_type)
@ -3039,59 +3039,61 @@ fn (mut c Amd64) assign_stmt(node ast.AssignStmt) {
} }
match node.op { match node.op {
.decl_assign, .assign { .decl_assign, .assign {
c.mov_store(.rdx, .rcx, size) c.mov_store(.rbx, .rcx, size)
} }
.plus_assign { .plus_assign {
c.add_reg(.rax, .rcx) c.add_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.minus_assign { .minus_assign {
c.sub_reg(.rax, .rcx) c.sub_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.and_assign { .and_assign {
c.bitand_reg(.rax, .rcx) c.bitand_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.mod_assign { .mod_assign {
c.mov(Amd64Register.rdx, i32(0)) // 64bits IDIV uses RDX:RAX
c.mod_reg(.rax, .rcx) c.mod_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.mult_assign { .mult_assign {
c.mul_reg(.rax, .rcx) c.mul_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.div_assign { .div_assign {
c.mov(Amd64Register.rdx, i32(0)) // 64bits IDIV uses RDX:RAX
c.div_reg(.rax, .rcx) c.div_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.xor_assign { .xor_assign {
c.bitxor_reg(.rax, .rcx) c.bitxor_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.or_assign { .or_assign {
c.bitor_reg(.rax, .rcx) c.bitor_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.right_shift_assign { .right_shift_assign {
c.shr_reg(.rax, .rcx) c.shr_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.left_shift_assign { .left_shift_assign {
c.shl_reg(.rax, .rcx) c.shl_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.unsigned_right_shift_assign { .unsigned_right_shift_assign {
c.sar_reg(.rax, .rcx) c.sar_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.boolean_and_assign { .boolean_and_assign {
c.bitand_reg(.rax, .rcx) c.bitand_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
.boolean_or_assign { .boolean_or_assign {
c.bitor_reg(.rax, .rcx) c.bitor_reg(.rax, .rcx)
c.mov_store(.rdx, .rax, size) c.mov_store(.rbx, .rax, size)
} }
else { else {
c.g.n_error('${@LOCATION} Unsupported assign instruction (${node.op})') c.g.n_error('${@LOCATION} Unsupported assign instruction (${node.op})')